Synopsys DesignWare with Quartus II

Hi,

I made a verilog module to instantiate each DW:module dw_add(/*autoarg*/

...

dw01_add# (ex_mul_partprod_bits)

u_add (.a(a), .b(b), .ci(ci), .sum(sum), .co(co) );

endmodule

Then I wrote a tcl script (for precision) to synt instance of DW:add_input_file ../dw_add.v

set options[list "width 10"]

setup_design -design dw01_add -overrides $options

compile

synthesize

auto_write -format verilog dw01_add.v

The first time I forgot to override parameter and I get a 4-bit adder (default value) which seemed to work on FPGA. But when I overrode parameter to 10 adder didn't work. DW netlist seems OK to me.

Regards,

Drackh