Stratix IV GXB Refclk IO standard settings

The error message is misleading. The real issue is discussed here:

http://www.altera.com/support/kdb/solutions/rd06252010_443.html

Cheers,

Dave

Hi Dave,

I would like to use the refclk input as the clock source for a pll in FPGA fabric and use one of the derived clock as a reference clock of a transceiver. Do you think that will be a problem?

Stratix IV handbook seems to suggest that this is feasible. On vol 2, section I, chapter 2, p.g. 2-5, it seems to have both the clock path to fabric and the clock path back to the transceiver.

In p.g. 2-8, ITB section, the last sentence from paragraph 1 confirms the clock path to fabric.

In p.g. 2-9, the first paragraph confirms the clock path to transceiver.

Am I reading this right? or is it that I have to do something to enable all these?

Thanks,

Hua

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I would like to use the refclk input as the clock source for a pll in FPGA fabric and use one of the derived clock as a reference clock of a transceiver. Do you think that will be a problem?

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This works fine. In some cases you'll get a warning about the possibility of increased jitter (I think it was due to cascading of PLLs).

Try it on the board and see how you go.

Cheers,

Dave

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This works fine. In some cases you'll get a warning about the possibility of increased jitter (I think it was due to cascading of PLLs).

Try it on the board and see how you go.

Cheers,

Dave

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That's what I did in the compiled project and got those fitting errors. Is there any other constraints I need to add to make it work?

Thanks,

Hua

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From the Example 2 on p.g. 2-14, I suspect that I have to add location constraints for specify which PLL to use...

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I didn't have to provide a location constraint. Though I am also routing the reference clock to a transceiver block - perhaps that makes a difference.

Cheers,

Dave

Hi Dave, Hi Hua,

In my current design (Stx IV EP4SGX230 as well), I'm using a PLL derived clock as reference clock for some transceiver blocks and it works fine.

Nevertheless, unlike what you would like to do, my PLL ref clock source for this derived clock is provided by a PLL dedicated clock input pin (Left PLL or Right PLL according to the GXB location side). This simply confirm the handbook p.g. 2-9, first paragraph (PLL output clock path to transceiver).

Regarding the PLL reference clock source, the handbook doesn't say much about the dedicated transceiver refclock pin connectivity to the the global clock network. The p.g. 2-8, ITB section, last sentence from paragraph 1 is a bit ambiguous to me. What does exactly mean "the clock logic in the FPGA fabric" ? If the term "clock logic" designates the global clock network, it's fine and your GXB clocking scheme is possible (and I guess it is).

Anyway, I don't know all your board constraints but I would simply recommend you to use a path as "straight" as possible from your ref clock input pin to your GXB RX CDRs or CMU PLLs ref clock input to avoid jitter amplification (refer to handbook p.g. 2-3, table2.2 "Input Reference Clock Source").

A last word about the location constraint: If your design uses transceiver channels on both sides of your FPGA, you have to duplicate the transceiver reference clock source on your board and to separately route to the reference clock input on each side. Indeed, there is no internal path through the device from one side to the other side.

Regards

Oliver

Thank you Oliver. I know my clocking scheme is a little bit odd but we are using Altera dev board to prototype a design and the clock I want to use (with the right clock frequency) is unfortunately tied to a refclk to a GXB. I have to use this clock to generate clocks for FPGA fabric and a refclk for another GXB.... Once we got our own board build this situation will go away.

Cheers,

Hua