Honored Contributor
Honored ContributorHi Dave, Hi Hua,
In my current design (Stx IV EP4SGX230 as well), I'm using a PLL derived clock as reference clock for some transceiver blocks and it works fine. Nevertheless, unlike what you would like to do, my PLL ref clock source for this derived clock is provided by a PLL dedicated clock input pin (Left PLL or Right PLL according to the GXB location side). This simply confirm the handbook p.g. 2-9, first paragraph (PLL output clock path to transceiver). Regarding the PLL reference clock source, the handbook doesn't say much about the dedicated transceiver refclock pin connectivity to the the global clock network. The p.g. 2-8, ITB section, last sentence from paragraph 1 is a bit ambiguous to me. What does exactly mean "the clock logic in the FPGA fabric" ? If the term "clock logic" designates the global clock network, it's fine and your GXB clocking scheme is possible (and I guess it is). Anyway, I don't know all your board constraints but I would simply recommend you to use a path as "straight" as possible from your ref clock input pin to your GXB RX CDRs or CMU PLLs ref clock input to avoid jitter amplification (refer to handbook p.g. 2-3, table2.2 "Input Reference Clock Source"). A last word about the location constraint: If your design uses transceiver channels on both sides of your FPGA, you have to duplicate the transceiver reference clock source on your board and to separately route to the reference clock input on each side. Indeed, there is no internal path through the device from one side to the other side. Regards Oliver
