Stratix IV GXB Refclk IO standard settings

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I would like to use the refclk input as the clock source for a pll in FPGA fabric and use one of the derived clock as a reference clock of a transceiver. Do you think that will be a problem?

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This works fine. In some cases you'll get a warning about the possibility of increased jitter (I think it was due to cascading of PLLs).

Try it on the board and see how you go.

Cheers,

Dave