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Altera_Forum's avatar
Altera_Forum
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13 years ago

Stratix iv FPGA interface with ADC

Hi,

We are using 4 ADCs(Analog to Digital converter) interfacing to Stratix EP4SGX230 FPGA. Each ADC is using 40 LVDS pairs and 10 control signals(2.5V) . When I instantiate ADC1/ADC2/ADC3/ADC4 independently all are working fine. But , When I instantiate All four ADCs the programming is failing. Any combination of three ADCs(for e.g ADC1, ADC2 and ADC3 or ADC2, ADC3 and ADC4 or ADC1 , ADC2 and ADC4) are programming properly and working fine. When I instantiate the 4th ADC the programming is failing.

Can any body please help me in this why the programming is failing.

Regards

Praveen

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    When I instantiate All four ADCs the programming is failing....

    Can any body please help me in this why the programming is failing.

    --- Quote End ---

    What do you mean by failing?

    Does this design work correctly in simulation? If it does, then I would suspect something more like a hardware issue, for example, a power supply failing to supply enough current.

    Try a test where all four ADCs are included in the design, but the controls for each ADC are configured such that they are all disabled on power up (if such an option is possible). Then try enabling one ADC at a time, two ADCs, three ADCs, and finally four ADCs. If the last option also causes a failure, then look at your power supplies in more detail.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Dave,

    Thanks for the reply.

    In simulation, the design is working correctly.

    When I reduced the ADC width to 7 bit (Each ADC is using 28 LVDS pairs) then I am able to program All the ADCs and also working fine.

    When I include all the ADC width to 10 bit (Each ADC is using 40 LVDS pairs)then programming is failing at 97%.

    The programming is always failing when the LVDS pairs increase more than 120.for e.g ADC 1 , ADC2 ADC3 is 9 bit ( 36 LVDS each ) and ADC4 is 3 bit (12 LVDS) the programming is successful and working fine. but if I increase the ADC4 to 4 bit(16 LVDS pairs)then the programming is failing at 97%.

    Is there any limitation of using LVDS pairs in stratix iv FPGA?

    Regards

    Praveen
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    In simulation, the design is working correctly.

    --- Quote End ---

    Ok, then you're looking for a hardware issue.

    --- Quote Start ---

    When I reduced the ADC width to 7 bit (Each ADC is using 28 LVDS pairs) then I am able to program All the ADCs and also working fine.

    When I include all the ADC width to 10 bit (Each ADC is using 40 LVDS pairs)then programming is failing at 97%.

    --- Quote End ---

    Did you look at the power supplies during this time? Eg. the 2.5V LVDS power rail or the FPGA core power supply?

    --- Quote Start ---

    Is there any limitation of using LVDS pairs in stratix iv FPGA?

    --- Quote End ---

    No, but you must have a power supply capable of delivering the current required for the design.

    Take your simulation, and provide toggling signals on each of the ADC inputs. Generate a .vcd file and perform a PowerPlay analysis on that file. See what Quartus predicts the power requirements of the design to be. Then check the power supply rating on your board.

    Cheers,

    Dave