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In simulation, the design is working correctly.
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Ok, then you're looking for a hardware issue.
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When I reduced the ADC width to 7 bit (Each ADC is using 28 LVDS pairs) then I am able to program All the ADCs and also working fine.
When I include all the ADC width to 10 bit (Each ADC is using 40 LVDS pairs)then programming is failing at 97%.
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Did you look at the power supplies during this time? Eg. the 2.5V LVDS power rail or the FPGA core power supply?
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Is there any limitation of using LVDS pairs in stratix iv FPGA?
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No, but you must have a power supply capable of delivering the current required for the design.
Take your simulation, and provide toggling signals on each of the ADC inputs. Generate a .vcd file and perform a PowerPlay analysis on that file. See what Quartus predicts the power requirements of the design to be. Then check the power supply rating on your board.
Cheers,
Dave
Honored Contributor
