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Altera_Forum
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13 years ago

Stratix iv FPGA interface with ADC

Hi, We are using 4 ADCs(Analog to Digital converter) interfacing to Stratix EP4SGX230 FPGA. Each ADC is using 40 LVDS pairs and 10 control signals(2.5V) . When I instantiate ADC1/ADC2/ADC3/ADC...
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Altera_Forum
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13 years ago

Hi Dave,

Thanks for the reply.

In simulation, the design is working correctly.

When I reduced the ADC width to 7 bit (Each ADC is using 28 LVDS pairs) then I am able to program All the ADCs and also working fine.

When I include all the ADC width to 10 bit (Each ADC is using 40 LVDS pairs)then programming is failing at 97%.

The programming is always failing when the LVDS pairs increase more than 120.for e.g ADC 1 , ADC2 ADC3 is 9 bit ( 36 LVDS each ) and ADC4 is 3 bit (12 LVDS) the programming is successful and working fine. but if I increase the ADC4 to 4 bit(16 LVDS pairs)then the programming is failing at 97%.

Is there any limitation of using LVDS pairs in stratix iv FPGA?

Regards

Praveen