Source code assignments using altera_attribute

Can anyone tell me if it's possible to assign a different Stratix III D6_DELAY value to each member of an output buss in source code? I'm using Verilog.

It has to be in the source code because the project I'm dealing with uses a `define to select different configurations of/for the same project. The output delays depend on the particular configuration.

I've been trying to do something like this so far but without much luck:

(* altera_attribute = "-name D6_DELAY 5" *) output LVDS_TXD_PCB;

this is rejected but in any case would assign a global delay - I actually want a tailored delay per output.

Thanks,