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Altera_Forum
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14 years ago

Source code assignments using altera_attribute

Can anyone tell me if it's possible to assign a different Stratix III D6_DELAY value to each member of an output buss in source code? I'm using Verilog. It has to be in the source code because...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Error was caused by a tab character so now to find out if I can tailor a delay per output from source code. Sorry for the sudden barrage of posts!