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Altera_Forum's avatar
Altera_Forum
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17 years ago

SOPC error "cpu1/instruction_master: Base Address for sysid conflicts with jtag_uart"

I use SOPC to bulid a multiple processors system.

But if I use DDR SDRAM as PSC A2S56D40CTP-G5 and generate. Then there are some errors about

"Error: cpu1/instruction_master: Base Address for pll must be a multiple of its span 0x40."

and "Error: cpu1/instruction_master: Base Address for sysid conflicts with jtag_uart."

But if I choose the DDR SDRAM as JEDEC DDR-400 256Mb x8 and generate successful.

Why this happen?

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Are you using the Auto assign base address feature to help resolve address conflicts?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I set local interface clock frequency as "full" instead "half". The errors are not occured longer.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I get a very similar error....

    cpu_0/instruction_master: Base Addresss for pll conflicts with slow_peripheral_bridge/s1

    cpo_0/data_master: Base Address for pll conflicts with slow_peripheral_bridge/s1

    This error occurs after the...

    Info:Starting generation...

    ...message which occurs quite some time after clicking the generate button. There are no address conflicts according to the information that is displayed in usual window. Whether or not I use "Automatically generate" the base addresses I get this error, although the automatically generate generally gives me a heap of other problems as it's not very clever.

    Oh, additionally, the pll is a component that hangs of the slow peripheral bridge. This makes it very difficult for me to understand an address conflict since the bridge occupies the cpu address world and the pll can only occupy the bridge address world. How can they possibly have conflicting base addresses?!?!?!

    I've looked through the .sopc file and can find no corruption and no conflicts. I've tried renaming both components to make sure there isn't some legacy rubbish floating around and the error changes names accordingly. Tried changing both addresses, which also makes no difference.

    Is this just a tools bug??? Or am I missing something obvious??!'

    Cheers
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well in the end I just repeated my design in a new project and it worked fine. I checked the two SOPC systems next to each other on the screen and compared all peripheral options. Identical! So reckon this must have been a tool funny!!

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It's happening to me too.. very annoying. I'm using SOPC Builder 9.1 Build 222. I also have refresh problem when I'm scrolling the screen.

    --- Quote Start ---

    Well in the end I just repeated my design in a new project and it worked fine. I checked the two SOPC systems next to each other on the screen and compared all peripheral options. Identical! So reckon this must have been a tool funny!!

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Did anyone get a proper solution to this? I got bitten by this one yesterday. Changing the local clock got rid of the error but that doesn't seem right. I also checked all the addresses against another version that generates correctly and there is no difference.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Me too stung by the same bug. Any solutions please?? Kind of desperate urgency!

    No address conflicts seen by the naked eye in the SOPC base address panel!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    This is kind of bug in the software i guess. Manual assignment solves the problem. But still,

    W H Y ?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Folks:

    After several successful iterations of building up a design, I added a clk crossing bridge and this bug just occurred in (10.1) my design too.

    Found a useful hint in QII9.0 rel notes (pg 30, link below)... I suppose this bug persists.

    http://www.altera.com/literature/rn/rn_qts_90.pdf?gsa_pos=3&wt.oss_r=1&wt.oss="base%20address%20for"%20"must%20be%20a%20multiple%20of%20its%20span"

    I suppose the answer is to manually rework the address space. Sweet.

    Jerry
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I get a very similar error....

    cpu_0/instruction_master: Base Addresss for pll conflicts with slow_peripheral_bridge/s1

    cpo_0/data_master: Base Address for pll conflicts with slow_peripheral_bridge/s1

    This error occurs after the...

    This occurs because memory is a slow peripheral as compared to the nios2 clock.So if you want to remove any clocking problems u have 2 options

    1. Either use a clock crossing bridge as suggested in one post to remove the clock crossing issues

    2. use the ddr clock for all the other peripherals.

    I used the ddr clock.There is an example design avialable for it.You can read about it in the ddr memory documentation for external memory interface.