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I get a very similar error....
cpu_0/instruction_master: Base Addresss for pll conflicts with slow_peripheral_bridge/s1
cpo_0/data_master: Base Address for pll conflicts with slow_peripheral_bridge/s1
This error occurs after the...
This occurs because memory is a slow peripheral as compared to the nios2
clock.So if you want to remove any clocking problems u have 2 options
1. Either use a clock crossing bridge as suggested in one post to remove the clock crossing issues
2. use the ddr clock for all the other peripherals.
I used the ddr clock.There is an example design avialable for it.You can read about it in the ddr memory documentation for external memory interface.
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