Honored Contributor
Honored ContributorI get a very similar error....
cpu_0/instruction_master: Base Addresss for pll conflicts with slow_peripheral_bridge/s1 cpo_0/data_master: Base Address for pll conflicts with slow_peripheral_bridge/s1 This error occurs after the... Info:Starting generation... ...message which occurs quite some time after clicking the generate button. There are no address conflicts according to the information that is displayed in usual window. Whether or not I use "Automatically generate" the base addresses I get this error, although the automatically generate generally gives me a heap of other problems as it's not very clever. Oh, additionally, the pll is a component that hangs of the slow peripheral bridge. This makes it very difficult for me to understand an address conflict since the bridge occupies the cpu address world and the pll can only occupy the bridge address world. How can they possibly have conflicting base addresses?!?!?! I've looked through the .sopc file and can find no corruption and no conflicts. I've tried renaming both components to make sure there isn't some legacy rubbish floating around and the error changes names accordingly. Tried changing both addresses, which also makes no difference. Is this just a tools bug??? Or am I missing something obvious??!' Cheers
