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Altera_Forum
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17 years ago

SOPC error "cpu1/instruction_master: Base Address for sysid conflicts with jtag_uart"

I use SOPC to bulid a multiple processors system. But if I use DDR SDRAM as PSC A2S56D40CTP-G5 and generate. Then there are some errors about "Error: cpu1/instruction_master: Base Address for p...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Folks:

After several successful iterations of building up a design, I added a clk crossing bridge and this bug just occurred in (10.1) my design too.

Found a useful hint in QII9.0 rel notes (pg 30, link below)... I suppose this bug persists.

http://www.altera.com/literature/rn/rn_qts_90.pdf?gsa_pos=3&wt.oss_r=1&wt.oss="base%20address%20for"%20"must%20be%20a%20multiple%20of%20its%20span"

I suppose the answer is to manually rework the address space. Sweet.

Jerry