Sine wave to Digital clock..

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y is the sine wave

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very unlikely!

Where y is originated from? I guess it's from a digital input pin, it can't represent an analog signal.

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very unlikely!

Where y is originated from? I guess it's from a digital input pin, it can't represent an analog signal.

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"y" is generated from an external function generator and inputted to the FPGA.

x is the output, which is supposed to be the sine wave after cutting its top and buttom.

I am not clear on what it is you are trying to do.

Are you trying to convert an analogue Voltage representing a sine wave into a square wave clock for use inside an FPGA?

You must do this externally to the FPGA with something like a Schmitt trigger or other circuity

FPGA's are digital only e.g. LVTTL, CMOS Levels etc

yes, but I thought I would be able to do the following:

when sinewave > fpga threashold , fpga will output 1.

when sinewave < fpga threashold , fpga will output 0.

so if I use a sinewave with a minimum value = 0, that is a normal sinewave with a positive offset, the fpga will act as if its cutting the upper and lower edges of the sinewave and outputs a clock..

isnt that right?

If you have a sinewave described with N bits (all positive values as you say) the MSB (most significant bit) of your sinewave will be your clock signal.

Cheers

OD

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yes, but I thought I would be able to do the following:

when sinewave > fpga threashold , fpga will output 1.

when sinewave < fpga threashold , fpga will output 0.

so if I use a sinewave with a minimum value = 0, that is a normal sinewave with a positive offset, the fpga will act as if its cutting the upper and lower edges of the sinewave and outputs a clock..

isnt that right?

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Hi sonaiko,

you have to keep in mind the maximum allowed I/O voltage ( depends on the Device family). Negative voltage should be avoided ( could damage your device). But with this restriction it should work. I'm not sure, but maybe your duty cycle is not exactly 50 %.

There is no need to implement a "slicer" inside the FPGA, the I/O cell will do it .

I'd say it will probably work as long as the signal on the pin stays within the limits in the device datasheet.

The duty cycle will depend on the actual signal levels and the logic thresholds of the device. If it's a slow/noisy signal you might get multiple transitions as the signal crosses the logic threshold so you'll probably have to debounce the input (debounce methods have been discussed elsewhere on the forums).

Others with more knowledge on the subject might be able to comment on possible increased power dissipation.