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yes, but I thought I would be able to do the following:
when sinewave > fpga threashold , fpga will output 1.
when sinewave < fpga threashold , fpga will output 0.
so if I use a sinewave with a minimum value = 0, that is a normal sinewave with a positive offset, the fpga will act as if its cutting the upper and lower edges of the sinewave and outputs a clock..
isnt that right?
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Hi sonaiko,
you have to keep in mind the maximum allowed I/O voltage ( depends on the Device family). Negative voltage should be avoided ( could damage your device). But with this restriction it should work. I'm not sure, but maybe your duty cycle is not exactly 50 %.
There is no need to implement a "slicer" inside the FPGA, the I/O cell will do it .
Honored Contributor
