Simulation yielding different results when changing top-level entity

Hi, I'm sorry if the question is silly but I'm new to quartus.

I have a project called HACK (an attempt to create Nand2Tetris' project in an actual FPGA board). It has the following pertinent files:

halfAdder.vhd
testHalfAdder.vhd
HACK.vhd

testHalfAdder is a testbench that instantiates the halfAdder component and tests it. HACK instantiates halfAdder in a way that doesn't actually make any sense, but just to force it to be compiled for now.

After creating halfAdder.vhd, I created halfFullAdder.vhd and added it to quartus testbenches list via Assignments->Settings->Simulation. I also checked the box to make simulation run automatically after compilation.

If I set halfAdder.vhd to be the top-level entity, everything runs fine and my simulation works. If i then set my top-level entity to be HACK, then the overall compilation works, but the simulation shows only undefined signals and exits with an error.

Am I doing something wrong or is this a bug? If I'm doing something wrong, how to correct it?

Thanks so much for any help.

halfAdder code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfAdder is
    Port (
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        sum : out STD_LOGIC; 
                  carry : out STD_LOGIC
    );
end halfAdder;

architecture Behavioral of halfAdder is
begin
    sum <= a xor b;
    carry <= a and b;
end Behavioral;

testHalfAdder code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testHalfAdder is
end entity testHalfAdder;

    architecture logic of testHalfAdder is
        
        component halfAdder is
            PORT(
                a : in STD_LOGIC;
                b : in STD_LOGIC;
                sum : out STD_LOGIC;
                carry : out STD_LOGIC);
        end component;

        signal in1 : STD_LOGIC;
        signal in2 :  STD_LOGIC;
        signal os : STD_LOGIC;
        signal oc : STD_LOGIC;

    begin

        DUT : halfAdder
            port map (
            a => in1,
            b => in2,
            sum => os,
            carry => oc
            );

        process
            variable i, j: integer;
				constant delay_time : time := 2 ps;
        begin

            for i in 0 to 1 loop
                for j in 0 to 1 loop
                    in1 <= std_logic'value(integer'image(i));
                    in2 <= std_logic'value(integer'image(j));
                    wait for delay_time;
                    if (os /= (in1 xor in2) or oc /= (in1 and in2)) then
                        report "in1=" & std_logic'image(in1) &
                        ", in2=" & std_logic'image(in2) &
                        ", os=" & std_logic'image(os) &
                        ", oc=" & std_logic'image(oc) severity error;
                    end if;
                end loop;
            end loop;

        end process;

    end architecture logic;

HACK code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HACK is
    Port (
        a : in STD_LOGIC;
        b : in STD_LOGIC;
        sum : out STD_LOGIC; 
	carry : out STD_LOGIC
    );
end HACK;

architecture Behavioral of HACK is

	component halfAdder is
		PORT(
			a : in STD_LOGIC;
			b : in STD_LOGIC;
			sum : out STD_LOGIC;
			carry : out STD_LOGIC);
	end component;


begin

    HA : halfAdder
	 port map (
		a => a,
		b => b,
		sum => sum,
		carry => carry
	);

	 
end Behavioral;

halfAdder working simulation:

halfAdder broken simulation after setting HACK to top level entity: