Forum Discussion
ocraM
New Contributor
New ContributorSimulation yielding different results when changing top-level entity
Hi, I'm sorry if the question is silly but I'm new to quartus. I have a project called HACK (an attempt to create Nand2Tetris' project in an actual FPGA board). It has the following pertinent file...
HACK.vhd is not a testbench. All it does is instantiate halfAdder. It doesn't provide any stimulus to halfAdder so you won't see anything in a simulation.
sstrell
Super Contributor
Super ContributorHACK.vhd is not a testbench. All it does is instantiate halfAdder. It doesn't provide any stimulus to halfAdder so you won't see anything in a simulation.
ocraMI see, I thought that testbenches were supposed to be always compiled and instantiated, but it seems that is not the case.
After you pointed me to the right direction i researched a bit and it seems the common practice is to simply define the desired testbench as a top-level entity when you want it to compile and run(?)
Thanks for the help
