Forum Discussion
ocraM
New Contributor
New ContributorSimulation yielding different results when changing top-level entity
Hi, I'm sorry if the question is silly but I'm new to quartus. I have a project called HACK (an attempt to create Nand2Tetris' project in an actual FPGA board). It has the following pertinent file...
HACK.vhd is not a testbench. All it does is instantiate halfAdder. It doesn't provide any stimulus to halfAdder so you won't see anything in a simulation.
sstrell
Super Contributor
Super ContributorCorrect. A testbench is a top-level design that instantiates a DUT and usually has no top-level I/O since it does not need to be implemented in hardware through synthesis. The reference to compilation here is that it must be able to compile in the simulation tool, not necessarily in the synthesis tool (Quartus).
