Honored ContributorHi everybody
I see that from the next release of QUARTUS II the simulator will not be supported and Altera reccomends to use ModelSim. As far as I know ModelSim is suitable for VERILOG and VHDL designes. So my question is: is there a way to simulate AHDL designes with the next release of QUARTUSII? Any informations is welcome. Marco
Honored Contributor2 Options:
1. you can similate post P&R netlists in modelsim. This is slow and not what you want when what you really want is RTL simulation 2. Stop writing stuff in the old, unsupported (by anyone other than altera, and even they want rid of it), unportable AHDL language.Honored ContributorActually there is a 3rd option:
dont download the new version of quartus.Honored ContributorThanks for your answer,
I think that the only real option is the second: I will switch to VERILOG even if I feel very confortable with AHDL, but,unfortunately, as you point out, it is a propriertary language.Honored ContributorDo not do it.
Do yourself a favor use SystemVerilog or VHDL2008. Do NOT use Verilog.Honored ContributorHi Amilcar,
please can you explain the reason of your warning?Honored ContributorProbably because of all the great validation stuff that you can do in VHDL or SystemVerilog.
Honored ContributorYou need to type a LOT in verilog to get things done. And the more you type the more prone you are for errors. You are a lot more productive with the other two languages. Both provide you with packages, and other nice stuff like assertions. And both are fully supported with Quartus II.
For me one of THE biggest advantages it that my code does not have a single "include" statement. For me include statements in HDL are like "goto" in software. Every software development book out there tells you to avoid "goto", and my experience in HDL tells me that "include" statements that plage normal verilog code will give you problems at some point. My code does not have any because of the cool packages feature. But the list of benefits is a lot longer. Just google for it. If you liked this answer please add to my reputation :)Honored Contributorthat's funny, all the Verilog people tell me VHDL is a lot more verbose than Verilog.
you can also do a post-map simulation rather than post-fit using an output HDL netlist into ModelSim, but as Tricky said its more of a workaround than a way forward.Honored ContributorSorry but I only have one answer to those people: BULLSH**T
I have years of experience with both languages and VHDL2008 is my personal favorite. But for simulation, if you have the $$$ to buy modelsim DE (yes, only modelsim DE fully supports all of SystemVerilog's assertion features) SystemVerilog is better. Verilog is very verbose, and in a bad way, take a look at port declaration for instance: first declare the ports, then declare their direction, then declare wires. That is a 3 time repetition in my book :) In SystemVerilog or VHDL2008 (or '93) you only do it once.Honored ContributorThanks everybody for your opinions.
Just a comment to Amilcar: It seems that you are referring to Verilog95 and not to the current version Verilog2001. In Verilog 2001 it is possible to declare ports and data types at once! ... or am I wrong? Marco
