Simulation in the next QUARTUS II releases

Sorry but I only have one answer to those people: BULLSH**T

I have years of experience with both languages and VHDL2008 is my personal favorite. But for simulation, if you have the $$$ to buy modelsim DE (yes, only modelsim DE fully supports all of SystemVerilog's assertion features) SystemVerilog is better.

Verilog is very verbose, and in a bad way, take a look at port declaration for instance: first declare the ports, then declare their direction, then declare wires. That is a 3 time repetition in my book :)

In SystemVerilog or VHDL2008 (or '93) you only do it once.