Simulating VHDL test bench using Modelsim

1. Create your waveform vector file in Quartus II

2. Export this file to vhdl test bench (file->export)

3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera.

chooose compile test bench in native link settings panel, click test benches, click new,

chosse any name for test bench, in test bench entity write: <your_top_level_entity>vhd_vec_tst

in instance name write : i1

chosee the file generated in step 1 in test bench files.

3. Compile your project.

4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation.

After this steps quartus ii opens modelsim an starts the simulation.

I get the following message in the transcript panel:

# Invalid time string specified: # Could not find Wave window Invalid time string specified:

here is my test bench :

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE WORK.pipeline_package.ALL;

ENTITY register_file_tb_ent IS

END register_file_tb_ent;

ARCHITECTURE register_file_tb_arch OF register_file_tb_ent IS

COMPONENT register_file_ent

PORT(

pd_read: IN std_logic;

pd_source1: IN register_type;

pd_source2: IN register_type;

clock: IN std_logic;

flush: IN std_logic;

ex_store: IN std_logic;

ex_destination: IN register_type;

ex_data: IN std_logic_vector(31 downto 0);

source1_data: OUT std_logic_vector(31 downto 0);

source2_data: OUT std_logic_vector(31 downto 0)

);

END COMPONENT;

SIGNAL pd_read: std_logic;

SIGNAL pd_source1: register_type;

SIGNAL pd_source2: register_type;

SIGNAL clock: std_logic:= '0';

SIGNAL flush: std_logic;

SIGNAL ex_store: std_logic;

SIGNAL ex_destination: register_type;

SIGNAL ex_data: std_logic_vector(31 downto 0);

SIGNAL source1_data: std_logic_vector(31 downto 0);

SIGNAL source2_data: std_logic_vector(31 downto 0);

CONSTANT CYCLE : TIME := 50 us;

BEGIN

DUT: register_file_ent port map( pd_read, pd_source1, pd_source2, clock, flush, ex_store, ex_destination, ex_data, source1_data, source2_data);

clock <= NOT clock AFTER CYCLE/2;

PROCESS

BEGIN

flush <= '0';

pd_read <= '0';

pd_source1 <= reg0;

pd_source2 <= reg0;

ex_store <= '0';

ex_destination <= reg0;

ex_data <= ZERO;

wait for CYCLE;

ex_store <= '1';

ex_destination <= reg0;

ex_data <= "00000000000000010000000001010001";

wait for CYCLE;

ex_store <= '1';

ex_destination <= reg1;

ex_data <= "00000000000000000000000000000001";

wait for CYCLE;

ex_store <= '0';

pd_read <= '1';

pd_source1 <= reg0;

pd_source2 <= reg1;

wait for CYCLE;

ex_store <= '0';

pd_read <= '1';

pd_source1 <= reg0;

pd_source2 <= reg1;

wait for CYCLE;

END PROCESS;

END register_file_tb_arch;

CONFIGURATION register_file_tb_config OF register_file_tb_ent IS

FOR register_file_tb_arch

FOR ALL : register_file_ent

USE ENTITY WORK.register_file_ent(register_file_arch);

END FOR;

END FOR;

END register_file_tb_config;

What is a .vwf file? I can not find it at the source folder. is it generate automatically when we compile the vhdl file?

--- Quote Start ---

I get the following message in the transcript panel:

# Invalid time string specified: # Could not find Wave window Invalid time string specified:

--- Quote End ---

I did have excatly the same problem just like yours. I am using ACTEL Libero and ModelSim Actel to do the wave simulation

the thing is, as soon as I open the ModelSim, after some compiling, there is always an error message appeared on the transcript window:# invalid time string specified

then the wave window is just blank

can someone here tell me whats going on with the software?:(