Simulating VHDL test bench using Modelsim

1. Create your waveform vector file in Quartus II

2. Export this file to vhdl test bench (file->export)

3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera.

chooose compile test bench in native link settings panel, click test benches, click new,

chosse any name for test bench, in test bench entity write: <your_top_level_entity>vhd_vec_tst

in instance name write : i1

chosee the file generated in step 1 in test bench files.

3. Compile your project.

4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation.

After this steps quartus ii opens modelsim an starts the simulation.