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Altera_Forum's avatar
Altera_Forum
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17 years ago

Simulating VHDL test bench using Modelsim

can anyone tell me the steps to follow in order to simulate my vhdl test bench with modelsim-altera? I had type my test bench with Quartus II and save the file.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Sorry. I have attach the pictures. the 1st picture is the view of the wave window. the 2nd one is the view of wave window preferences. It is disable. so I think I maybe some how have changes the setting of the software so causing the wave windows didn't show anythings. how to restore the default setting of the modelsim? I reinstall the modelsim but the problem still occur...