Simulating VHDL test bench using Modelsim

here is my test bench :

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE WORK.pipeline_package.ALL;

ENTITY register_file_tb_ent IS

END register_file_tb_ent;

ARCHITECTURE register_file_tb_arch OF register_file_tb_ent IS

COMPONENT register_file_ent

PORT(

pd_read: IN std_logic;

pd_source1: IN register_type;

pd_source2: IN register_type;

clock: IN std_logic;

flush: IN std_logic;

ex_store: IN std_logic;

ex_destination: IN register_type;

ex_data: IN std_logic_vector(31 downto 0);

source1_data: OUT std_logic_vector(31 downto 0);

source2_data: OUT std_logic_vector(31 downto 0)

);

END COMPONENT;

SIGNAL pd_read: std_logic;

SIGNAL pd_source1: register_type;

SIGNAL pd_source2: register_type;

SIGNAL clock: std_logic:= '0';

SIGNAL flush: std_logic;

SIGNAL ex_store: std_logic;

SIGNAL ex_destination: register_type;

SIGNAL ex_data: std_logic_vector(31 downto 0);

SIGNAL source1_data: std_logic_vector(31 downto 0);

SIGNAL source2_data: std_logic_vector(31 downto 0);

CONSTANT CYCLE : TIME := 50 us;

BEGIN

DUT: register_file_ent port map( pd_read, pd_source1, pd_source2, clock, flush, ex_store, ex_destination, ex_data, source1_data, source2_data);

clock <= NOT clock AFTER CYCLE/2;

PROCESS

BEGIN

flush <= '0';

pd_read <= '0';

pd_source1 <= reg0;

pd_source2 <= reg0;

ex_store <= '0';

ex_destination <= reg0;

ex_data <= ZERO;

wait for CYCLE;

ex_store <= '1';

ex_destination <= reg0;

ex_data <= "00000000000000010000000001010001";

wait for CYCLE;

ex_store <= '1';

ex_destination <= reg1;

ex_data <= "00000000000000000000000000000001";

wait for CYCLE;

ex_store <= '0';

pd_read <= '1';

pd_source1 <= reg0;

pd_source2 <= reg1;

wait for CYCLE;

ex_store <= '0';

pd_read <= '1';

pd_source1 <= reg0;

pd_source2 <= reg1;

wait for CYCLE;

END PROCESS;

END register_file_tb_arch;

CONFIGURATION register_file_tb_config OF register_file_tb_ent IS

FOR register_file_tb_arch

FOR ALL : register_file_ent

USE ENTITY WORK.register_file_ent(register_file_arch);

END FOR;

END FOR;

END register_file_tb_config;

What is a .vwf file? I can not find it at the source folder. is it generate automatically when we compile the vhdl file?