PrivateIsland
New Contributor
1 year agoSimulating inferred DSP in Questa using Intel DSP simulation library
When inferring a DSP in Verilog, what is the recommended method to simulate an actual DSP from the Quartus EDA simulation library without having to create the DSP as an IP block?
I assume I need to simulate an intermediate compiled output, and I'm hoping to retain as much of the surrounding logic as possible.
This is a general question across multiple Altera FPGAs and Quartus versions, but I'm currently trying to do this with Quartus Pro, Questa Intel Starter Edition, and the C10X.
Thank you