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Robert_PIN_ASAP's avatar
Robert_PIN_ASAP
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Simulating inferred DSP in Questa using Intel DSP simulation library

When inferring a DSP in Verilog, what is the recommended method to simulate an actual DSP from the Quartus EDA simulation library without having to create the DSP as an IP block? I assume I need to...
Simulation
HubertG's avatar
HubertG
Icon for Contributor rankContributor
2 years ago

Hi PrivateIsland,


If you are convenient, could you please provide your design to us to look into the problem for a better support to you ?


Thanks

Hubert


Robert_PIN_ASAP's avatar
Robert_PIN_ASAP
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you for the replies and interest in my question.

I was hoping to read that there is an established Quartus tool flow to produce an intermediate output of my inferred DSPs and memories that could be simulated in Questa using Intel simulation IP libraries along with my behavioral RTL / Verilog. This would be similar to the simulation environment if I had created the IP blocks using the IP Parameter Editor.

No worries. I believe I can create some custom scripts to produce my desired result.

Thank you again. You can close this one out.