Forum Discussion
Robert_PIN_ASAP
Occasional Contributor
Occasional ContributorSimulating inferred DSP in Questa using Intel DSP simulation library
When inferring a DSP in Verilog, what is the recommended method to simulate an actual DSP from the Quartus EDA simulation library without having to create the DSP as an IP block? I assume I need to...
HubertG
Contributor
ContributorHello, I apologize for the delay in getting back to you. Please allow me a bit more time to review the solution, and I will follow up with you shortly.
FvMSuper Contributor
Hi,
you don't need to take special prerequisites to simulate inferred (or explicitely instantiated) DSP blocks. Simply simulate your synthesizable HDL with a suitable test bench.
