Simulating Designs with Lower-Level Qsys Systems

Yes. I typically start by running the msim_setup.tcl script generated in the simulation/ folder, and then edit that so that vcom builds my top-level testbench. The msim_setup.tcl script has a variable to define the top-level entity.

Take a look at msim_setup.tcl and if you cannot figure it out, ask for more help.

Cheers,

Dave

Hi Dave.

What software are you using?

Mine is Quartus II 64-bit Version 13.1 Web Edition, with ModelSim Starter Edition 10.1d.

I'm following the procedure outlined in the "Simulating Designs with Lower-Level Qsys Systems" document and

can Run a Nios II Simulation from the Nios II SBT, but only if Qsys generates a Verilog testbench simulation model.

Repeating the process with a VHDL simulation model produces ModelSim Transcript warnings about submodules in protected region and failure to copy a file.

# -- Compiling architecture RTL of niosii_system_mm_interconnect_0_cmd_xbar_demux

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# ** Warning: C:/LL2/niosii_system/testbench/niosii_system_tb/simulation/submodules/mentor/altera_merlin_traffic_limiter.sv(38): in protected region.

.....

.....

# -- Compiling entity niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo

# ** Error: (vcom-1935) Unable to move temporary file C:/LL2/software/lower_level_qsys/obj/default/runtime/sim/mentor/libraries/nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/_temp/vlog6arnds to C:/LL2/software/lower_level_qsys/obj/default/runtime/sim/mentor/libraries/nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/_primary.dbs.

#

# No such file or directory. (errno = ENOENT)

# ** Error: C:/LL2/niosii_system/testbench/niosii_system_tb/simulation/submodules/niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vho(46): VHDL Compiler exiting

# C:/altera/13.1/modelsim_ase/win32aloem/vcom failed.

The temporary folder exists, but there are no files in it.

Thanks,

B_T

I haven't tried VHDL simulation with a NIOS II processor.

I have successfully used Modelsim-ASE for some VHDL simulation. Some of the SystemVerilog files are still allowed in this mode, and other files are generated as .vho (compiled source). Unfortunately, Altera's support for single-language simulation with Modelsim-ASE is not that great (its not an easy problem, so you cannot really blame them). When I write tutorials for use with Modelsim-ASE, I try to stick with a single language, i.e., SystemVerilog, since that is what Altera's latest code is written using.

If I need to perform mixed-language simulation, I use Modelsim-SE, since I have access to it (via the Mentor University Program).

Cheers,

Dave

Hi Dave,

Do you think simulation of a VHDL design with an embedded Nios II processor would be achievable if I were to switch to ModelSim-SE and used its mixed-language simulation?

(the simulations I have run successfully have been launched from Nios II SBT using the Nios II processor as the top level design and verilog for simulation code)

Thanks,

B_T

--- Quote Start ---

Do you think simulation of a VHDL design with an embedded Nios II processor would be achievable if I were to switch to ModelSim-SE and used its mixed-language simulation?

--- Quote End ---

Simulation with Modelsim-SE should work.

If it does not, then its likely an error in the Altera simulation scripts, not Modelsim-SE. In that case, you can usually read the error messages in the Modelsim console and determine the source of the error, eg., I've seen cases of missing -L arguments to vsim.

Cheers,

Dave

Thanks Dave.

I've now got the simulation working in ModelSim-Altera with a top level VHDL project. I started with a blank project and followed the guidelines in the " Simulating Designs with Lower-Level Qsys Systems" document.

My new project has shorter folder names than the example provided. I suspect it may be an issue with a file/path buffer overrun somewhere.

I found an older thread which had a similar problem:

http://www.alteraforum.com/forum/showthread.php?t=37564 (http://www.alteraforum.com/forum/showthread.php?t=37564)

Although the VHDL simulation is running in ModelSim-Altera, the transcript gives a performance warning:

# Loading Qsys_inst_reset_bfm.altera_avalon_reset_source(behavioral)

# ** Warning: Design size of 141 instances exceeds ModelSim ALTERA recommended capacity.

# This may because you are loading cell libraries which are not recommended with

# the ModelSim Altera version. Expect performance to be adversely affected.

B_T