Simulating Designs with Lower-Level Qsys Systems

Thanks Dave.

I've now got the simulation working in ModelSim-Altera with a top level VHDL project. I started with a blank project and followed the guidelines in the " Simulating Designs with Lower-Level Qsys Systems" document.

My new project has shorter folder names than the example provided. I suspect it may be an issue with a file/path buffer overrun somewhere.

I found an older thread which had a similar problem:

http://www.alteraforum.com/forum/showthread.php?t=37564 (http://www.alteraforum.com/forum/showthread.php?t=37564)

Although the VHDL simulation is running in ModelSim-Altera, the transcript gives a performance warning:

# Loading Qsys_inst_reset_bfm.altera_avalon_reset_source(behavioral)

# ** Warning: Design size of 141 instances exceeds ModelSim ALTERA recommended capacity.

# This may because you are loading cell libraries which are not recommended with

# the ModelSim Altera version. Expect performance to be adversely affected.

B_T