Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Simulating Designs with Lower-Level Qsys Systems

I have used the Nios II SBT for Eclipse "Run as Nios II ModelSim" command to generate a simulation environment where the Qsys system is the top-level entity. Now I would like to simulate a design in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Dave,

Do you think simulation of a VHDL design with an embedded Nios II processor would be achievable if I were to switch to ModelSim-SE and used its mixed-language simulation?

(the simulations I have run successfully have been launched from Nios II SBT using the Nios II processor as the top level design and verilog for simulation code)

Thanks,

B_T