Simulating Designs with Lower-Level Qsys Systems

I haven't tried VHDL simulation with a NIOS II processor.

I have successfully used Modelsim-ASE for some VHDL simulation. Some of the SystemVerilog files are still allowed in this mode, and other files are generated as .vho (compiled source). Unfortunately, Altera's support for single-language simulation with Modelsim-ASE is not that great (its not an easy problem, so you cannot really blame them). When I write tutorials for use with Modelsim-ASE, I try to stick with a single language, i.e., SystemVerilog, since that is what Altera's latest code is written using.

If I need to perform mixed-language simulation, I use Modelsim-SE, since I have access to it (via the Mentor University Program).

Cheers,

Dave