Simulating Designs with Lower-Level Qsys Systems

Hi Dave.

What software are you using?

Mine is Quartus II 64-bit Version 13.1 Web Edition, with ModelSim Starter Edition 10.1d.

I'm following the procedure outlined in the "Simulating Designs with Lower-Level Qsys Systems" document and

can Run a Nios II Simulation from the Nios II SBT, but only if Qsys generates a Verilog testbench simulation model.

Repeating the process with a VHDL simulation model produces ModelSim Transcript warnings about submodules in protected region and failure to copy a file.

# -- Compiling architecture RTL of niosii_system_mm_interconnect_0_cmd_xbar_demux

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# ** Warning: C:/LL2/niosii_system/testbench/niosii_system_tb/simulation/submodules/mentor/altera_merlin_traffic_limiter.sv(38): in protected region.

.....

.....

# -- Compiling entity niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo

# ** Error: (vcom-1935) Unable to move temporary file C:/LL2/software/lower_level_qsys/obj/default/runtime/sim/mentor/libraries/nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/_temp/vlog6arnds to C:/LL2/software/lower_level_qsys/obj/default/runtime/sim/mentor/libraries/nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo/_primary.dbs.

#

# No such file or directory. (errno = ENOENT)

# ** Error: C:/LL2/niosii_system/testbench/niosii_system_tb/simulation/submodules/niosii_system_mm_interconnect_0_nios2_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo.vho(46): VHDL Compiler exiting

# C:/altera/13.1/modelsim_ase/win32aloem/vcom failed.

The temporary folder exists, but there are no files in it.

Thanks,

B_T