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Altera_Forum's avatar
Altera_Forum
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10 years ago

Simple counter/memory logic- question- Help needed

Hello,

I am implementing a simple memory RAM in VHDL.

logic: We have a 24 bit input data....need to split into two 12 bits data, and append 4 bits in the MSB side, and fill the memory......

compile error: ** Fatal: (vsim-3421) Value 1440 is out of range 0 to 1439.# Time: 28820 ns Iteration: 0 Process: /single_ended_tb/UUT/READ_PROCESS File: E:/PROJECT/PROGRAMS/TESTING_SIMULATION/INPUT_LOGIC/Single_Ended/newlogic_rings_April14/single_ended.vhd

attaching the program for your reference.

any help would be appreciated..

Kind Regards,

Manoj

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    In your simulation, your addresses are going over the limit of the memory array size. I suggest debugging on the waveform.

    As a hint - your check on counter limits is an even number. But count_addr_2 is always odd, and so will never reset (maybe you want to use > rather than = for the comparison).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thank you Tricky!. I fixed it as per your reply, and its working fine now.