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Altera_Forum
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11 years ago

Simple counter/memory logic- question- Help needed

Hello, I am implementing a simple memory RAM in VHDL. logic: We have a 24 bit input data....need to split into two 12 bits data, and append 4 bits in the MSB side, and fill the memory...... ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

In your simulation, your addresses are going over the limit of the memory array size. I suggest debugging on the waveform.

As a hint - your check on counter limits is an even number. But count_addr_2 is always odd, and so will never reset (maybe you want to use > rather than = for the comparison).