New ContributorSimple connection betwenn two ethernet ports on DE2-115
Hi everyone!
I'm trying to connect the two ethernet ports on DE2-115. Basically, I just want to bypass the signal between the two ports without any code/decode protocol. I'am trying to perform this task just in the PHY/MAC layers. I already tryied some codes, but i didn't manage it. Could anyone help me on this?
One of my used codes is:
module com_eth0_eth1(
clock_50,
enet0_tx_data,
enet0_gtx_clk,
enet0_tx_clk,
enet0_tx_en,
enet0_tx_er,
enet0_rx_data,
enet0_rx_clk,
enet0_rx_dv,
enet0_rx_er,
enet1_tx_data,
enet1_gtx_clk,
enet1_tx_clk,
enet1_tx_en,
enet1_tx_er,
enet1_rx_data,
enet1_rx_clk,
enet1_rx_dv,
enet1_rx_er
);
// Ethernet0
output enet0_gtx_clk, enet0_tx_clk;
input enet0_rx_clk;
// Ethernet1
output enet1_gtx_clk, enet1_tx_clk;
input enet1_rx_clk;
// Saídas
// Ethernet 0
output [3:0] enet0_tx_data;
output enet0_tx_en, enet0_tx_er;
// Ethernet 1
output [3:0] enet1_tx_data;
output enet1_tx_en, enet1_tx_er;
// Entradas
// Ethernet 0
input [3:0] enet0_rx_data;
input enet0_rx_dv, enet0_rx_er;
// Ethernet 1
input [3:0] enet1_rx_data;
input enet1_rx_dv, enet1_rx_er;
reg [3:0] enet0_tx_data;
reg enet0_tx_en, enet0_tx_er;
reg [3:0] enet1_tx_data;
reg enet1_tx_en, enet1_tx_er;
reg enet0_gtx_clk, enet1_gtx_clk, enet0_tx_clk, enet1_tx_clk;
reg ledr0, ledr1, ledg0, ledg1;
// Funcionamento do circuito
always @(posedge enet0_rx_clk or posedge enet1_rx_clk)
begin
enet0_gtx_clk <= enet1_rx_clk;
enet1_gtx_clk <= enet0_rx_clk;
enet0_tx_clk <= enet1_rx_clk;
enet1_tx_clk <= enet0_rx_clk;
enet1_tx_en <= enet0_rx_dv;
enet1_tx_data <= enet0_rx_data;
enet1_tx_er <= enet0_rx_er;
enet0_tx_en <= enet1_rx_dv;
enet0_tx_data <= enet1_rx_data;
enet0_tx_er <= enet1_rx_er;
end
endmodule
