Signal Tap Problem: Some signals have jitter

Dear all,

I have a 100 Mhz 32 bit width FIFO master interface working on an Cyclone V Altera FPGA. The 100 Mhz fifoclk comes from a connected USB 3.0 interface, which acts as a bridge between the FPGA and a host pc. THe goal of this setup is to investigate the USB 3.0 interface for speed and response timings.

For this I want to look at the data and control signals which are arriving at the FPGA FIFO master and are thrown back to the USB interface. To look at this signal I need to have a sampling clock with at least 200 MHz to satisfy shannons theorem. So I created a 200 Mhz clock which is by a pll and the pll is driven by the cyclone V delopement board (Terasic Cyclone V GX Starter Board) onboard 50 Mhz clock. Between the pll and the signal tap 2 there is also a ALTCLKCTRL to get this clk as global clock working.

However nearly half of the signals which I am looking at are having terrible jitter. I wonder if the problem lies in that the 50 Mhz clock from the devlopment board is not accurately in phase with the 100 Mhz clock from the USB 3.0 interface. But on the other hand even signals which come form the cyclone v dev board are showing this jitter.

Can you help me investigate this problem?

I also tried so set these clocks as clocks in the sdc but the compiler tells me that they cannot be matched with a port:

Warning (332174): Ignored filter at al_mc600.sdc(9): clock100_net could not be matched with a port

Warning (332049): Ignored create_clock at al_mc600.sdc(9): Argument <targets> is an empty collection

Info (332050): create_clock -name sigClk -period 5.0 [get_ports {clock100_net}]

Warning (332174): Ignored filter at al_mc600.sdc(11): clk100 could not be matched with a port

Warning (332049): Ignored create_clock at al_mc600.sdc(11): Argument <targets> is an empty collection

Info (332050): create_clock -name clk100 -period 5.0 [get_ports {clk100}]

Below is a screenshot of the signal tap signals. For example the signals Data(9:15) can not have such a signal fluctuation until it is first asserted in the near of sample 0. RESET_N must be alway 1 and mem_rstn should also always be 1. :cry:

https://alteraforum.com/forum/attachment.php?attachmentid=14746&stc=1