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Altera_Forum
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8 years ago

Signal Tap Problem: Some signals have jitter

Dear all, I have a 100 Mhz 32 bit width FIFO master interface working on an Cyclone V Altera FPGA. The 100 Mhz fifoclk comes from a connected USB 3.0 interface, which acts as a bridge between the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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There is no need to drag in Shannon ...

Just use the 100 MHz USB clock as the clock of your SignalTap system.

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Thank you for your answer. But please can you explain why Shannon is not needed in this case?

Thank you