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Honored Contributor
Honored ContributorSignal Tap Problem: Some signals have jitter
Dear all, I have a 100 Mhz 32 bit width FIFO master interface working on an Cyclone V Altera FPGA. The 100 Mhz fifoclk comes from a connected USB 3.0 interface, which acts as a bridge between the ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- There is no need to drag in Shannon ... Just use the 100 MHz USB clock as the clock of your SignalTap system. --- Quote End --- Thank you for your answer. But please can you explain why Shannon is not needed in this case? Thank you
