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Altera_Forum
Honored Contributor
8 years agoSignal Tap Problem: Some signals have jitter
Dear all, I have a 100 Mhz 32 bit width FIFO master interface working on an Cyclone V Altera FPGA. The 100 Mhz fifoclk comes from a connected USB 3.0 interface, which acts as a bridge between the ...
Altera_Forum
Honored Contributor
8 years agoNyquist-Shannon theorem should be applied when converting analog signal to digital. In your case you already are working with digital signals. So as josyb said no need to involve any theorems here. Jitter that you are seeing is from timing violations (Setup and Hold) which are caused because you are sampling your signals with clock which is asynchronous to them. For signaltap as a sampling clock you have to chose synchronous clock to your signals and thats it.