Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

I actually have a similar issue, but for a Stratix V. I Synthesize my design, then I go and add SignalTap (verified it is added by seeing it checked in the SignalTap Settings page). I then compile my design. The design has no timing violations. What I notice is that sometimes everything is fine and SignalTap loads and I can connect to my design. Other times after programming I see "Invalid JTAG Configuration" Then I have to go back and remove SignalTap, re-compile and add it back again. Does anyone else know if this is typical? It is almost like something is corrupt during the build process, or the board doesn't fully get programmed.

If anyone has good common practices of using SignalTap in a design I would appreciate pointers. Do you have to remove/re-add SignalTap every time you make a change to your design?

Thanks.

The message "Instance not found" is telling you that this design does not contain this instance of SignalTap II.

Once you've created a SignalTap II instance, you need to add it to your project, and then re-synthesize the design.

The SignalTap II GUI normally asked you if you want to add this instance to your project. If you said no, then you can still add it, you just have to go to the Assignments->Settings menu, and under Category select SignalTap II Logic Analyzer, set the path to the instance, and check the check-button to use it.

Cheers,

Dave

It is possible that you're getting this message because you have a timing fault on the connection between the SignalTap logic and the configuration logic (which is connected to the JTAG pins on the device). This is represented by special pins called altera_reserved_tck / tms / tdi / tdo.

Do you have timing constraints set on these pins (for example on the altera_reserved_tck pin)? If you don't then quartus won't report violations. Recent versions of Quartus have high speed default constraints on these pins but older versions of Quartus don't.

I don't have the correct constraints to hand but will try and find them if they are missing in your design. You need to constrain altera_reserved_tck to 24MHz and altera_reserved_tdo to I think 3ns external delay (might be 5ns)

Which Quartus version are you using?

So I have the following constraints:

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdi]

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tms]

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_ntrst]

set_output_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdo]

set_clock_groups -asynchronous

-group {altera_reserved_tck}

** There are more constraints for the rest of the design, but if you think I am missing one please let me know.

On most of the Stratix V boards I'm aware of the On-Board USB-Blaster II design is used (check the logo near the USB connector).

This clocks the TCK line at 24MHz so you will need tighter constraints.

The constraints I use are similar to these:

create_clock -name altera_reserved_tck  -period "24 MHz"
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_output_delay -clock altera_reserved_tck -clock_fall 3 

The second constraint makes Quartus put the output registers nearer the TDO pin, which is where the timing problems normally appear. The actual values you put in the input and output delays depends on your board design, but the smallest value which Quartus can route is safe.

You may also want to try preventing Quartus from promoting TCK to a global clock (there's an assignment for that but I can't remember the details right now) as that causes problems on some devices.

If you can use 13.0 then it has better default constraints built in which should get correct timing for soft logic JTAG agents such as SignalTap.

Thanks for the suggestions. I have temporarily switched to using the USB Blaster (instead of the BlasterII) and that seems to resolve the issue. That leads me to believe that I do have a 10 MHz vs. 24 MHz timing constraint error as you pointed out. I don't yet have access to 13.0, but I will try with your recommended constraints and report back if it works better.

Thanks for the help.

You could alternatively turn the clock speed down on USB-Blaster II with this command:

jtagconfig --setparam <cable-id> JtagClock 16M

The cable only supports some cable speeds, 6M, 15M and 24M are the usual ones.