Honored Contributor
Honored ContributorIt is possible that you're getting this message because you have a timing fault on the connection between the SignalTap logic and the configuration logic (which is connected to the JTAG pins on the device). This is represented by special pins called altera_reserved_tck / tms / tdi / tdo.
Do you have timing constraints set on these pins (for example on the altera_reserved_tck pin)? If you don't then quartus won't report violations. Recent versions of Quartus have high speed default constraints on these pins but older versions of Quartus don't. I don't have the correct constraints to hand but will try and find them if they are missing in your design. You need to constrain altera_reserved_tck to 24MHz and altera_reserved_tdo to I think 3ns external delay (might be 5ns) Which Quartus version are you using?
