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Altera_Forum
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12 years ago

Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

Hi, I'm trying to use SignalTap in the Quartus II IDE and after setting up USB Blaster according to some online tutorial, (it seems to be working in the sense that the "Hardware Setup" tab identifies...
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Altera_Forum
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12 years ago

So I have the following constraints:

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdi]

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tms]

set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_ntrst]

set_output_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdo]

set_clock_groups -asynchronous

-group {altera_reserved_tck}

** There are more constraints for the rest of the design, but if you think I am missing one please let me know.