Signal Tap II - Invalid JTAG Configuration (using USB Blaster) (Cyclone IV)

On most of the Stratix V boards I'm aware of the On-Board USB-Blaster II design is used (check the logo near the USB connector).

This clocks the TCK line at 24MHz so you will need tighter constraints.

The constraints I use are similar to these:

create_clock -name altera_reserved_tck  -period "24 MHz"
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_input_delay -clock altera_reserved_tck -clock_fall 3 
set_output_delay -clock altera_reserved_tck -clock_fall 3 

The second constraint makes Quartus put the output registers nearer the TDO pin, which is where the timing problems normally appear. The actual values you put in the input and output delays depends on your board design, but the smallest value which Quartus can route is safe.

You may also want to try preventing Quartus from promoting TCK to a global clock (there's an assignment for that but I can't remember the details right now) as that causes problems on some devices.

If you can use 13.0 then it has better default constraints built in which should get correct timing for soft logic JTAG agents such as SignalTap.