signal II tap issue with I/O BUS

Hello and thanks for any help.

I am using signal II tap to debug an I/O Bus between FPGA and DSP. My design works fine in timing simulation and I do see my "BUS~result" showing count up to the DSP synchronized to a common clock between the two devices.

However in signal II tap my bus is always showing <0000>, the weird thing is that if I tap into the count signal that feeds the BUS signal I do see the count up working but not on the actual BUS signal.

Any remarks are greatly appreciated.

thx,

Mowa...