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Altera_Forum
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15 years ago

signal II tap issue with I/O BUS

Hello and thanks for any help. I am using signal II tap to debug an I/O Bus between FPGA and DSP. My design works fine in timing simulation and I do see my "BUS~result" showing count up to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Are you sure the count signal is feeding the output pins? are these pins bidirectiona? if so are you actually driving them?