Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

signal II tap issue with I/O BUS

Hello and thanks for any help. I am using signal II tap to debug an I/O Bus between FPGA and DSP. My design works fine in timing simulation and I do see my "BUS~result" showing count up to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

May be you better start with a fresh signaltap.

I asked about bidirectional pins because a pitfall may occur if you are not driving it correctly at the right time. It could be the DSP chip is driving it with zeros.