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Altera_Forum's avatar
Altera_Forum
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15 years ago

signal II tap issue with I/O BUS

Hello and thanks for any help. I am using signal II tap to debug an I/O Bus between FPGA and DSP. My design works fine in timing simulation and I do see my "BUS~result" showing count up to the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for the reply,

I am pretty sure I am driving them and the timing simulation confirms, the bus is bidirectional. I wonder if there is something funny about the PINS in S2T?