signal as loop termination condition

Hi all ;

I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board.

I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: loop must terminate within 10,000 iterations" (ID: 10536).

This is my main code.

library ieee;use ieee.std_logic_1164.all;
use work.time_issues.all;
entity DD is 
    port (clk:in std_logic);
end entity DD;
    
architecture behav of DD is
    constant step_count  : integer := 2500000; --#step's for 10ms at 50Mhz clk
    begin
    time_delay(clk,step_count);
end architecture behav;

And this is the package code.

library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
PACKAGE time_issues IS
    PROCEDURE time_delay (signal t_clk:in std_logic; step_count: in integer);
END time_issues;
    
PACKAGE BODY time_issues IS
    PROCEDURE time_delay(signal t_clk:in std_logic; step_count: in integer) IS
    
        variable count : integer;
        variable count_out : integer;
    BEGIN
        count:=0;
        loop
            if (t_clk) then
                count := count + 1; 
            else
                count := count + 0; 
            end if;
            exit when (count = step_count);
        end loop;
        
        
    END PROCEDURE time_delay;
END PACKAGE BODY time_issues;

At the definition of error (ID: 10536) it is written that if i use a signal for loop termination conditon this may happen. But then if i want to synchronise my procedure with clk signal how would i do it.

I tried to use "wait until clk;" but appears to be i cannot use wait statement in a procedure.

Any help ? Thanks