Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

signal as loop termination condition

Hi all ; I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board. I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Of course my design will have some outputs but in the begining i wanted to handle and finish that time delay issue. I'll take your sentence "For synthesisable code you probably never want to use procedures." as a guideline for synthesizable code.

Thanks a lot.