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Altera_Forum
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11 years ago

signal as loop termination condition

Hi all ; I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board. I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

So there is no way to synchronise a procedure with clock signal. But what should i do then for a just 1 line code in order to achieve a time delay. Entity instantiation may be?