signal as loop termination condition

I think you need to stop. Take a step back.

Your code currently does nothing on a real FPGA, because it has no outputs. Therefore, it is useless for synthesis.

You can synchronise a procedure with a signal just fine. You can also use any wait statments you want in a procedure. But this is all for simulation. For synthesis you need to think about the logic you want to create, and then describe it. For synthesisable code you probably never want to use procedures.

You need a counter, in a synchronous process.

signal count : unsigned(10 downto 0);
process(clk)
begin
    if rising_edge(clk) then
        
        if count < SOME_NUMBER then
            count <= count + 1;
        end if;
        
        if count = SOME_NUMBER then
            --do something
        end if;
    end if;
end process;